1. Field of the Invention
The present invention relates to a communication scheme and system equipped with an LSI device that provides an interface between a high-speed transmission line and a lower-speed device, and more particularly to a method and system for insertion and extraction of overhead in SONET/SDH (Synchronous Digital Hierarchy). The overhead is used on data transfer via a network as information for operation and administration of the network.
2. Description of the Prior Art
A conventional method and system for insertion and extraction of overhead in SONET or SDH have an LSI device in which every port has a frame-processing unit for interfacing to a high-speed line and an interface unit for interfacing to a lower-speed external device to perform insertion and extraction of the overhead present in a SONET/SDH frame; providing the LSI device with multiple ports has come to be an important issue. In particular, recent LSI devices have come to be highly functional, by performing numerous functions or having numerous channels, and communication capabilities are being implemented in a single IC.
Such an LSI device will now be described below; insertion and extraction of overhead will be described separately with reference to FIGS. 11 to 13 and FIGS. 14 to 16, respectively.
First, as shown in FIG. 11, for the STS-12c system, for example, an interface system that performs insertion of overhead has a frame processing unit 70 for processing frames in SONET/SDH. The frame processing unit 70 interfaces to a high-speed line. The interface system also has an overhead insertion interface unit 73 that interfaces to a lower-speed external device. The SONET/SDH frame processing unit 70 has a transport overhead (TOH) processor 71 for inserting overhead into a frame transmitted to the line and a path overhead (POH) processor 72; and the overhead insertion interface unit 73 has a TOH timing generator 74 that includes a function for generating timing for transmitting TOH data to the line, a function for generating timing for the external device to input TOH data, and a buffer function used in transmitting TOH data from the external device to the line; the overhead insertion interface unit 73 also has a POH timing generator 75 that generates timing for POH data in a way similar to the TOH timing generator 74.
The basic STS-1 SONET frame structure, transport overhead (TOH), and path overhead (POH) have been disclosed in JP-A-101009/1993 (FIGS. 3, 4, and 6) and other documents. The STS-3c system is a combination of three STS-1 systems, and STS-12c represents a frame size of a combination (concatenation) of four STS-3c systems; a detailed description will be omitted herein. The concatenation is well known, being disclosed in JP-A-278235/2000 and other documents.
Next, the operations of the interface system will be described. As shown in FIG. 11, when an A1-byte request pulse (a pulse for requesting the A1 byte allocated in the first row of overhead) is input as a frame timing pulse for establishing synchronization of frames from the frame processing unit 70 to the TOH timing generator 74 in the overhead insertion interface unit 73, the TOH timing generator outputs a TOH clock (TTOHCK) and a TOH framing pulse (TTOHFP) to the external device to request it to input 4-bit parallel TOH data (TTOH[3:0]), as shown in FIGS. 11 and 12. In FIG. 12, b1 in the TOH data (TTOH[3:0]) represents the first bit of each byte from A1 to Z0 in the first row of TOH in the frame; representations of the second to eighth bits are omitted. Since a TOH clock (5.184 MHz) is a frequency for inputting the 36 TOH bytes over a whole one-row span of overhead, the external device outputs a TOH enable signal (TTOHEN), plus 4-bit parallel TOH data, to the TOH timing generator 74 in synchronization with the TOH clock. As a result, the TOH timing generator 74 outputs TOH data to the frame processing unit 70, which inserts the TOH into the frame.
Similarly, as shown in FIG. 11, when a J1-byte request pulse, which is a pulse requesting the J1 byte that is a part of the path overhead (POH) and is allocated to the first byte of the payload, is input as a frame timing pulse from the frame processing unit 70 to the POH timing generator 75 in the overhead insertion interface unit 73, the POH timing generator 75 outputs a POH clock (TPOHCK) and a POH framing pulse (TPOHFP) to the external device to request it to input POH data (TPOH), as shown in FIGS. 11 and 13. In FIG. 13, b1 in the POH data represents the first bit of each byte from J1 to Z5 in the first column of POH in the frame; representations of the second to eighth bits are omitted. Since a POH clock (576 KHz) is a frequency for inputting the 1 POH byte over a whole one-byte span of overhead, the external device outputs the POH data in synchronization with the POH clock, together with a POH enable signal (TPOHEN), to the POH timing generator 75. As a result, the POH timing generator 75 outputs the POH data to the frame processing part 70, whereby the POH is inserted into the frame.
Next, as shown in FIG. 14, an interface system performing extraction of overhead is configured with circuits similar to those of the interface system shown in FIG. 11. More specifically, the interface system has a SONET/SDH frame processing part 80 that includes a transport overhead (TOH) processor 81 for interfacing to the high-speed line side to extract overhead from a frame received from the line and a path overhead (POH) processor 82, and an overhead extraction interface unit 83 for interfacing to a lower-speed external device. The overhead extraction interface unit 83 has a TOH timing generator 84 that includes a function for generating timing for receiving TOH data input from a line, a function for generating timing for outputting TOH data to the external device, and a buffer function used in receiving TOH data output from the line to the external device; and a POH timing generator 85 that generates timing for POH data in a way similar to the TOH timing generator 84.
Next, the operations of the interface unit will be described. As shown in FIG. 14, when an A1-byte pulse, which is a pulse requesting the A1 byte allocated to the first row of overhead, is input as a frame timing pulse for establishing synchronization of the frame from the SONET/SDH frame processing part 80 to the TOH timing generator 84 in the overhead extraction interface unit 83, the TOH timing generator 84 outputs a TOH clock (RTOHCK) and a TOH framing pulse (RTOHFP) to the external device, and receives TOH data from the frame processing unit 80, as shown in FIGS. 14 and 15. Since the TOH data is input and appears with fixed timing in every row, the TOH timing generator 84 receives it with the fixed timing in subsequent rows. In this example, two rows of TOH data can be stored and switched at every row. The TOH data is output as RTOH[3:0] from the TOH generator 84 to the external device. In FIG. 15, b1 in RTOH data [3:0] also represents a first bit of each byte from A1 to Z0 in the first row of TOH in the frame; representations of the second to eighth bits are omitted. TOH clock (5.184 MHz) is a frequency for outputting the 36 TOH bytes over a whole one-row span of overhead, so the TOH timing generator 84 outputs 4-bit parallel TOH data to the external device in synchronization with the TOH clock.
As a result, TOH data is output from the frame processing unit 80 to the TOH timing generator 84, whereby the overhead is extracted from the frame.
Similarly, as shown in FIG. 14, when a J1-byte pulse, which is a pulse requesting the J1 byte that is a part of the path overhead (POH) and is allocated to the first byte of the payload, is input as a frame timing pulse from the frame processing unit 80 to the POH timing generator 85 in the overhead extraction interface unit 83, the POH timing generator 85 outputs a POH clock (RPOHCK) and a POH framing pulse (RPOHFP) to the external device, together with POH data (RPOH), as shown in FIGS. 14 and 16. In FIG. 16, b1 in the POH data (RPOH) represents the first bit of each byte from J1 to Z5 in the first column of POH; representations of the second to eighth bits are omitted.
As a result, POH data is output from the frame processing unit 80 to the POH timing generator 85, whereby the POH is extracted from the frame.
In the TOH clock and POH clock transmitted from the overhead insertion interface unit 73 and the overhead extraction interface unit 83 to the external device, a blank span (shown in FIGS. 1, 2, 13, 15, and 16) indicates an idle span. That is, request data or valid data is indicated only by the clock.
The aforementioned conventional SONET/SDH overhead insertion and extraction method and system place TOH overhead data (each byte) at a fixed location in a frame, thereby enabling periodic insertion and extraction of TOH. In contrast to TOH overhead data, however, POH overhead data (each byte) is not placed at a fixed location. This is because byte J1 in the POH, which indicates the location where the Synchronous Payload Envelope (SPE) begins, is dynamically designated by a pointer contained in the TOH. Therefore, a phase difference arises between overhead data in TOH and overhead data in POH, so the TOH and POH must be inserted into and extracted from a frame with different timing. Accordingly, the overhead insertion and extraction interface units must handle TOH and POH separately. That is, these interface units must be provided separately.
As described above, the conventional overhead insertion and extraction method and system must provide separate terminals for TOH and POH, so each port, including the ports of an interface system, must have more terminals, a drawback that prevents the number of ports per LSI device from being increased.
In addition, the conventional overhead insertion and extraction method and system perform processing of transport overhead and path overhead separately, thus present a drawback that it cannot adjust frequencies on the overhead transmitting side, or the insertion interface unit.
Furthermore, the conventional overhead insertion and extraction method and system must provide a number of POH interface units equal to the number of channels supported to realize multi-channel frame, increasing the number of terminals, raising the unwelcome problem of whether to increase the size of the LSI device to accommodate the plurality of ports or decrease the number of ports that can be accommodated in an LSI device.